Pillgram::Audio: Difference between revisions

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Line 5: Line 5:
<code>/dts-v1/;
<code>/dts-v1/;
/plugin/;
/plugin/;
 
/ {
/ {
     compatible = "brcm,bcm2712", "brcm,bcm2711", "brcm,bcm2835";
     compatible = "brcm,bcm2712", "brcm,bcm2711", "brcm,bcm2835";
 
     fragment@0 {
     fragment@0 {
         target = <&i2s>;  // For RPi4
         target = <&i2s>;  // For RPi4
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         };
         };
     };
     };
 
     fragment@2 {
     fragment@2 {
             target-path = "/";
             target-path = "/";
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             };
             };
     };
     };
 
     fragment@3 {
     fragment@3 {
         target = <&i2c1>;
         target = <&i2c1>;
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             #size-cells = <0>;    /* No size cells for I2C devices */
             #size-cells = <0>;    /* No size cells for I2C devices */
             status = "okay";
             status = "okay";
 
             tlv320aic3110: tlv320aic3110@18 {
             tlv320aic3110: tlv320aic3110@18 {
                 compatible = "ti,tlv320aic3110", "ti,tlv320aic311x";  
                 compatible = "ti,tlv320aic3110", "ti,tlv320aic311x";  
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                 // system-clock-direction-out;          // Codec as master
                 // system-clock-direction-out;          // Codec as master
                 status = "okay";
                 status = "okay";
 
                 HPVDD-supply = <&vdd_3v3_reg>;
                 HPVDD-supply = <&vdd_3v3_reg>;
                 SPRVDD-supply = <&vdd_5v0_reg>;
                 SPRVDD-supply = <&vdd_5v0_reg>;
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                 IOVDD-supply = <&vdd_3v3_reg>;
                 IOVDD-supply = <&vdd_3v3_reg>;
                 DVDD-supply = <&codec_1v8_reg>;
                 DVDD-supply = <&codec_1v8_reg>;
 
                 clocks = <&mclk_external>;
                 clocks = <&mclk_external>;
                 clock-names = "mclk";
                 clock-names = "mclk";
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                 mclk-frequency = <12288000>;
                 mclk-frequency = <12288000>;
                 // gpio-controller;
                 // gpio-controller;
 
                 /* PLL configuration for 48kHz with 12.288MHz MCLK */
                 /* PLL configuration for 48kHz with 12.288MHz MCLK */
                 pll-p = <1>;
                 pll-p = <1>;
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                 pll-j = <7>;
                 pll-j = <7>;
                 pll-d = <1680>;
                 pll-d = <1680>;
 
                 reset-gpios = <&gpio 13 0>; // GPIO 13 as active high  
                 reset-gpios = <&gpio 13 0>; // GPIO 13 as active high  
                 reset-delay-us = <10000>;    /* 10ms delay */
                 reset-delay-us = <10000>;    /* 10ms delay */
 
                 // Debug properties
                 // Debug properties
                 debug;
                 debug;
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         };
         };
     };
     };
 
     fragment@5 {
     fragment@5 {
         target = <&sound>;
         target = <&sound>;
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             // simple-audio-card,bitclock-master = <&dailink0_master>;
             // simple-audio-card,bitclock-master = <&dailink0_master>;
             // simple-audio-card,frame-master = <&dailink0_master>;
             // simple-audio-card,frame-master = <&dailink0_master>;
 
             simple-audio-card,widgets =
             simple-audio-card,widgets =
                 "Microphone", "Mic Jack",
                 "Microphone", "Mic Jack",
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                 "MIC1LM", "Mic Jack";
                 "MIC1LM", "Mic Jack";
             status = "okay";
             status = "okay";
 
             simple-audio-card,cpu {
             simple-audio-card,cpu {
                 sound-dai = <&i2s>;
                 sound-dai = <&i2s>;
             };
             };
 
             dailink0_master: simple-audio-card,codec {
             dailink0_master: simple-audio-card,codec {
                 sound-dai = <&tlv320aic3110>;
                 sound-dai = <&tlv320aic3110>;
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                 mclk-fs = <256>; //*** added LAX
                 mclk-fs = <256>; //*** added LAX
             };
             };
         };
         };
     };
     };
 
     fragment@6 {
     fragment@6 {
         target-path = "/";
         target-path = "/";
Line 121: Line 120:
         };
         };
     };
     };
};
};
</code>
</code>

Revision as of 22:35, 8 January 2025

TLV320AIC3110

Schematics

Device Tree

/dts-v1/; /plugin/;

/ {

   compatible = "brcm,bcm2712", "brcm,bcm2711", "brcm,bcm2835";

   fragment@0 {
       target = <&i2s>;  // For RPi4
       __overlay__ {
           status = "okay";
           #sound-dai-cells = <0>;
           brcm,tx-channels = <2>;
           brcm,rx-channels = <2>;
       };
   };

   fragment@2 {
           target-path = "/";
           __overlay__ {
                   codec_1v8_reg: codec-1v8-reg {
                       compatible = "regulator-fixed";
                       regulator-name = "tlv320aic3104_1v8";
                       regulator-min-microvolt = <1800000>;
                       regulator-max-microvolt = <1800000>;
                       regulator-always-on;
                   };
           };
   };
 
   fragment@3 {
       target = <&i2c1>;
       __overlay__ {
           #address-cells = <1>; /* Single cell for I2C address */
           #size-cells = <0>;    /* No size cells for I2C devices */
           status = "okay";

           tlv320aic3110: tlv320aic3110@18 {
               compatible = "ti,tlv320aic3110", "ti,tlv320aic311x"; 
               reg = <0x18>;
               #sound-dai-cells = <0>;
               // system-clock-frequency = <12288000>;  // Codec clock config
               // system-clock-direction-out;           // Codec as master
               status = "okay";

               HPVDD-supply = <&vdd_3v3_reg>;
               SPRVDD-supply = <&vdd_5v0_reg>;
               SPLVDD-supply = <&vdd_5v0_reg>;
               AVDD-supply = <&vdd_3v3_reg>;
               IOVDD-supply = <&vdd_3v3_reg>;
               DVDD-supply = <&codec_1v8_reg>;

               clocks = <&mclk_external>;
               clock-names = "mclk";
               // system-clk-frequency = <12288000>;
               mclk-frequency = <12288000>;
               // gpio-controller;

               /* PLL configuration for 48kHz with 12.288MHz MCLK */
               pll-p = <1>;
               pll-r = <1>;
               pll-j = <7>;
               pll-d = <1680>;

               reset-gpios = <&gpio 13 0>; // GPIO 13 as active high 
               reset-delay-us = <10000>;     /* 10ms delay */

               // Debug properties
               debug;
               linux,debug;
           };
       };
   };

   fragment@5 {
       target = <&sound>;
       __overlay__ {
           compatible = "simple-audio-card";
           simple-audio-card,name = "TLV320AIC3110";
           simple-audio-card,format = "i2s";
           // simple-audio-card,bitclock-master = <&dailink0_master>;
           // simple-audio-card,frame-master = <&dailink0_master>;

           simple-audio-card,widgets =
               "Microphone", "Mic Jack",
               "Speaker", "Speaker Left",
               "Speaker", "Speaker Right";
           simple-audio-card,routing =
               "Speaker Left", "SPL",
               "Speaker Right", "SPR",
               "MIC1LP", "Mic Jack",
               "MIC1LM", "Mic Jack";
           status = "okay";

           simple-audio-card,cpu {
               sound-dai = <&i2s>;
           };

           dailink0_master: simple-audio-card,codec {
               sound-dai = <&tlv320aic3110>;
               clocks = <&mclk_external>;
               system-clock-frequency = <12288000>; //*** added LAX
               mclk-fs = <256>; //*** added LAX
           };
       };
   };

   fragment@6 {
       target-path = "/";
       __overlay__ {
           mclk_external: mclk_external {
               compatible = "fixed-clock";
               #clock-cells = <0>;
               clock-frequency = <12288000>; // 12.288 MHz
               clock-output-names = "mclk";
           };
       };
   };

};